Disturb-resistant non-volatile memory device using via-fill and etchback technique

ABSTRACT

A method of forming a disturb-resistant non volatile memory device includes providing a substrate and forming a first dielectric thereon, forming a first strip of material separated from a second strip of material from a first wiring material, and forming a second dielectric thereon to fill a gap between the first and second strips of material. Openings are formed in the second dielectric exposing portions of the first wiring material. Filing the openings by p+ polysilicon contact material, and then an undoped amorphous silicon material, and then a metal material. A second wiring structure is formed thereon to contact the metal material in the openings. Resistive switching cells are formed from the first wiring structure, the second wiring structure, the contact material, the undoped amorphous silicon material, and the metal material.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to and is a divisional application of U.S. application Ser. No. 13/339,939 filed on Dec. 29, 2011, which claims the benefit of provisional application 61/428,994 filed Dec. 31, 2010, commonly assigned, and incorporated by reference in their entirety herein.

BACKGROUND

The present invention is generally related to resistive switching devices. More particularly, embodiments according to the present invention provide a method and a structure for forming a resistive switching device. The present invention can be applied to non-volatile memory devices but it should be recognized that the present invention can have a much broader range of applicability.

The success of semiconductor devices has been mainly driven by an intensive transistor down-scaling process. However, as field effect transistors (FET) approach sizes less than 100 nm, problems such as short channel effect can degrade device performance. Moreover, such sub 100 nm device size can lead to sub-threshold slope non-scaling and also increases power dissipation. It is generally believed that transistor-based memories such as those commonly known as Flash may approach an end to scaling within a decade. Flash memory is one type of non-volatile memory device.

Other non-volatile random access memory (RAM) devices such as ferroelectric RAM (Fe RAM), magneto-resistive RAM (MRAM), organic RAM (ORAM), and phase change RAM (PCRAM), among others, have been explored as next generation memory devices. These devices often require new materials and device structures to couple with silicon-based devices to form a memory cell, which lack one or more key attributes. For example, Fe-RAM and MRAM devices have fast switching characteristics and good programming endurance, but their fabrication is not CMOS compatible and size is usually large. Power dissipation during switching for a PCRAM device is usually large. Organic RAM or ORAM is incompatible with large volume silicon-based fabrication and device reliability is usually poor.

From the above, a new semiconductor device structure and integration is desirable.

BRIEF SUMMARY OF THE PRESENT INVENTION

The present invention is directed to switching devices. More particularly, embodiments according to the present invention provide a method and a structure to form an array of switching devices. The present invention has been applied to forming a disturb-resistant non-volatile memory device using an amorphous silicon switching material. But it should be recognized that embodiments of the present invention can be applied to other devices.

In a specific embodiment, a method of forming a disturb-resistant non-volatile memory device is provided. The method includes providing a substrate having a surface region and forming a first dielectric material overlying the surface region of the semiconductor substrate. A first wiring material is deposited overlying the first dielectric material and a contact material is formed overlying the first wiring material. In a specific embodiment, the contact material includes doped polysilicon material. The method subjects the first wiring material and the contact material to a first patterning and etching process to separating a first strip of material from a second strip of material. In a specific embodiment, each of the first strip of material and the second strip of material include the first wiring material and the contact material. The first strip of material and the second strip of material are spatially oriented in a first direction in a specific embodiment. The method includes forming a thickness of a second dielectric material overlying the first strip of material, the second strip of material, and filling a gap region between the first strip of material and the second strip of material. In a specific embodiment, the method forms a first opening and a second opening in a portion of the thickness of the second dielectric material overlying the first strip of material, and forming a third opening and a fourth opening in a portion of the thickness of the second dielectric material overlying the second strip of material, and exposing a surface region of the contact material. A switching material comprising an amorphous silicon material is deposited overlying the thickness of second dielectric material and to at least partially fill each of the first opening, the second opening, the third opening, and the fourth opening. In a specific embodiment, the method subjects the switching material to an etch back process to remove the switching material overlying the second dielectric material while maintaining the switching material in each of the first opening, the second opening, the third opening, and the fourth opening. A second wiring material is formed overlying the switching material in each of the first opening, the second opening, the third opening, and the fourth opening in a specific embodiment.

In a specific embodiment, a method of forming a disturb-resistant non volatile memory device is provided. The method includes providing a first cell and a second cell. The first cell is formed from a first wiring structure, a second wiring structure, a switching material, and a contact material sandwiched between the first wiring structure and the second wiring structure. In a specific embodiment, the first wiring structure is spatially configured to extend in a first direction and the second wiring structure is spatially configured to extend in a second direction orthogonal to the first direction in a specific embodiment. In a specific embodiment, the switching material includes an amorphous silicon material, and the contact material can be a p+ polysilicon material. A first switching region formed in an intersecting region between the first wiring structure and the second wiring structure. The second cell is formed from the first wiring structure, the switching material, the contact material, and a third wiring structure. The third wiring structure is parallel to the second wiring structure. A second switching region is formed in an intersecting region between the first wiring structure and the third wiring structure. In a specific embodiment, at least the switching material and the contact material forms a coupling between the first cell and the second cell In a specific embodiment, the coupling is eliminated coupling by disposing the switching material in a first via opening associated with the first cell and in a second via opening associated with the second cell. The first via opening and the second via opening are isolated using a dielectric material to electrically and physically isolate the first switching region and the second switching region.

In a specific embodiment, a non-volatile memory device is provided. The device includes a substrate having a surface region and a first dielectric material overlying the surface region of the semiconductor substrate. The device includes at least a first cell and a second cell. In a specific embodiment, the first cell includes a first wiring structure extending in a first direction overlying the first dielectric material. A first contact region overlies the first wiring structure and a first switching region overlies the first contact region. The first contact region includes a p+ polysilicon material and the first switching region includes an amorphous silicon material in a specific embodiment. The first cell includes a second wiring structure extending in a second direction orthogonal to the first direction overlying the switching region. The second cell includes a second contact region comprising the p+ polysilicon material overlying the first wiring structure. A second switching region comprising the amorphous silicon material overlies the second contact region. The second cell includes a third wiring structure overlying the second switching region. The third wiring structure is separated from the second wiring structure and parallel to the second wiring structure. In a specific embodiment, a dielectric material is disposed at least in a region between the first switching region and the second switching region to electrically and physically isolate the first switching region and the second switching region. In other embodiment, the dielectric material is further disposed between a first region between the first contact region and the second contact region to further electrically and physically isolate the first contact region and the second region.

Many benefits can be achieved by ways of present invention. The present invention uses convention CMOS fabrication techniques to form a disturb resistant non-volatile memory array. Embodiments according to the present invention further provide an array of interconnected switching devices to be used in a high density memory device. Depending on the embodiment, one or more of these benefits can be achieved. One skilled in the art would recognize other variations, modifications, and alternatives.

SUMMARY OF THE DRAWINGS

FIG. 1 is a simplified diagram illustrating a resistive switching device according to an embodiment of the present invention.

FIG. 2 is a simplified diagram illustrating a conventional method of fabricating an array of switching devices.

FIGS. 3-14 a are simplified diagrams illustrating a method of forming a disturb-resistant memory device according to an embodiment of the present invention.

FIGS. 15-22 are simplified diagrams illustrating an alternative method of forming a disturb-resistant memory device according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The present invention is generally related to switching devices. More particularly, embodiments according to the present invention provide a method and a structure to form an array of switching devices. Various embodiments according to the present invention have been applied to forming a disturb-resistant non-volatile memory device using an amorphous silicon switching material. But it should be recognized that embodiments of the present invention can have other much broader range of applicability.

FIG. 1 is a simplified diagram illustrating a cross section of a resistive switching device 100. The resistive switching device includes a top wiring structure 102, a bottom wiring structure 104 and a switching element 108 disposed between the top wiring structure and the bottom wiring structure. In a crossbar array, the top electrode and the bottom electrode are arranged orthogonal to each other to form a highly interconnected structure. In this implementation, the top wiring structure and the bottom wiring structure can have a portion including a conductor material such as tungsten, copper, or aluminum that are commonly used in CMOS processing. The top wiring structure further includes a metal material in contact with the switching element. For a switching element using an amorphous silicon material, the metal material can be silver or other suitable metal materials. Other suitable metal materials can include gold, platinum, palladium, nickel, aluminum, and others, depending on the application. The silver material can be formed in a via structure connecting the amorphous silicon switching material to other portion of the top wiring structure. Again, for an amorphous silicon switching material, the bottom electrode can include a buffer layer 110 between the bottom wiring material and the switching material to provide desirable switching characteristics upon application of a voltage or a current to the top electrode or the bottom electrode. The buffer layer can be a doped silicon material such as a p+ doped polysilicon in a specific embodiment.

FIG. 2 illustrates three interconnected switching devices 202, 204, and 206 initially developed by the assignee of the present invention. As shown, each of the switching devices has a bottom stack 208 including a bottom electrode 210, amorphous silicon layer 212 and p+ polysilicon layer 214 disposed in a first direction 220. The top electrode 216 including silver material 218 is formed orthogonal to the bottom stack. In certain implementation, silver material 218 is disposed in a via structure in direct contact with the amorphous silicon material. For this interconnected structure, the inventor of the present invention determined that a parasitic leakage path 222 can form between adjacent cells in the first direction 220 during read, write, or erase cycles and cause cross-talk between adjacent cells or interconnected cells, as shown.

Embodiments of the present invention provide a method and a structure to form a non-volatile memory device having a silver/amorphous silicon material/bottom electrode configuration. The present method and structure provide a device that is more resistant to cross talk or disturb between adjacent cells during programming in a specific embodiment.

FIGS. 3-12 are simplified diagrams illustrating a method of forming a non-volatile memory device according to embodiments of the present invention. As shown in FIG. 3, the method includes a semiconductor substrate 302 having a surface region 304. The semiconductor substrate can be a silicon material, a silicon germanium substrate, silicon on insulator substrate, or others, depending on the application. In a specific embodiment, the substrate can also include one or more transistor devices formed thereon. The one or more transistor devices are operably coupled to the memory devices and control the memory devices in certain embodiment.

The method includes forming a first dielectric material 402 overlying the surface region of the substrate as shown in FIG. 4. The first dielectric material can be silicon dioxide, silicon nitride, low K dielectric, or a dielectric stack such as silicon oxide on silicon nitride on silicon oxide, commonly known as ONO, depending on the application. The first dielectric material can be formed using techniques such as chemical vapor deposition; including plasma enhanced chemical vapor deposition, physical vapor deposition or a combination depending on the application.

Referring to FIG. 5, the method includes forming a first wiring material 502 overlying the first dielectric material. The first wiring material can include common metal materials used in CMOS processing, such as tungsten, copper, or aluminum, and others. The first wiring material can further include one or more adhesion layer or diffusion barrier layer between the metal material and the first dielectric layer in a specific embodiment. The adhesion layer or diffusion barrier layer can be titanium, titanium nitride, tungsten nitride, titanium tungsten, or others depending on the embodiment.

As shown in FIG. 6, the method includes depositing a contact material 602 comprising a silicon material overlying the first wiring material. The silicon material can be a p+ polysilicon material in a specific embodiment. The p+ polysilicon material can be deposited using techniques such as chemical vapor deposition and precursor such as silane, disilane, or a suitable chlorosilane, and boron as a dopant in a specific embodiment. Deposition temperature can range from about 250 Degree Celsius to about 750 Degree Celsius depending on the process and precursors used. In certain embodiments, the deposition temperature can range from about 300 Degree Celsius to about 400 Degree Celsius. Depending on the application, the contact material can be optional.

As illustrated in FIG. 7, the method includes subjecting the contact material and the first wiring material to a first patterning and etching process to form a plurality of strips of material including a first strip of material 702 and a second strip of material 704 separated by a first void region 706 and exposing a surface region 708 of the first dielectric material. In a specific embodiment, each of the plurality of strips of material are spatially disposed in a first direction 710.

Referring to FIG. 8, the method includes depositing a thickness of a second dielectric material 802 overlying each of the plurality of strips of material and filling the void regions. In a specific embodiment, the second dielectric material can be the same as the first dielectric material and can include silicon dioxide, silicon nitride, low K dielectric, or a dielectric stack such as silicon oxide on silicon nitride on silicon oxide, commonly known as ONO, depending on the application. The second dielectric material can be formed using techniques such as chemical vapor deposition; including plasma enhanced chemical vapor deposition, physical vapor deposition or a combination. One skilled in the art would recognize other variations, modifications, and alternatives.

Referring to FIG. 9, the method includes subjecting the second dielectric material to a second pattering and etching process to form a plurality of via openings in a portion of the second dielectric material. As shown a first opening 902 and a second via opening 904 overly the first strip of material to expose a surface region of the contact material in the first strip of material. A third opening 906 and a fourth via opening 908 overly the second strip of material to expose a surface region of the contact material in the second strip of material. A surface region 910 of the second dielectric material is shown.

In some embodiments, via openings (e.g., 902-908) can have sidewalls that are substantially linear over the depth of the via openings. In other words, the sidewalls of the via can be a substantially a straight line extending from the top of the via to the bottom of the via, as illustrated at FIG. 10.

Referring to FIG. 10, the method includes depositing a switching material 1002 to at least partially fill each of the plurality of via openings (for example, first via opening 902, second via opening 904, third via opening 906, and fourth via opening 908) and overlying surface region 910 of the second dielectric material. A cross section view from direction 710 is shown in FIG. 10. Switching material 1002 includes an amorphous silicon material in a specific embodiment. The amorphous silicon material has an intrinsic semiconductor characteristic and further characterized by an electrical resistance depending on a voltage applied to the device. The amorphous silicon material can be deposited using techniques such as chemical vapor deposition and precursor such as silane, disilane, or a suitable chlorosilane in a specific embodiment. Deposition temperature is usually maintained between 250 Degree Celsius to about 500 Degree Celsius depending on the embodiment. In various embodiments, the amorphous silicon is also referred to as non-crystalline silicon (nc-Si). nc-Si non-volatile resistive switching devices may be fabricated using existing CMOS technologies. In an exemplary process, a mixture of silane (SiH4) (45 sccm) and Helium (He) (500 sccm) is used to form an a-Si layer with a deposition rate of 80 nm per minute (T=260° C., P=600 mTorr) during PECVD. In another exemplary process, a mixture of silane (SiH4) (190 sccm) and Helium (He) (100 sccm) is used to form an a-Si layer with a deposition rate of 2.8 A per second (T=380° C., P=2.2 Torr) during PECVD. In another exemplary process, silane (SiH4 80 sccm) or disilane is used to form an a-Si layer with a deposition rate of 2.8 nm per minute (T=585° C., P=100 mTorr) during LPCVD. Portions of poly-silicon grains may form during the LPCVD process and result in an amorphous-poly silicon film. In various embodiments, no p-type, n-type, or metallic impurities are intentionally added to the deposition chamber while forming the amorphous silicon material. Accordingly, when deposited, the amorphous silicon material is substantially free of any p-type, n-type or metallic dopants, i.e. the amorphous silicon material is undoped. In a specific embodiment, the p+ polysilicon material prevents an interfacial region to form between the amorphous silicon material and the first conductor material. The interface region can have excessive defect sites, which trap conductive particles, including charges, affecting proper switching.

In a specific embodiment, the method includes subjecting switching material 1002 to an etch back process to remove the switching material from the surface region of the second dielectric material, while the switching material is maintained in a portion 1102 of the each of the via openings in contact with the contact material as shown in FIG. 11. Depending on the application, the etch back process can be a reactive ion etch process in a plasma environment and stops at the surface region of the second dielectric material. Alternatively, the switching material may be subjected to a chemical mechanical polishing process to remove the switching material from the surface region of the second dielectric material while maintaining the switching material in the via opening in contact with the contact material in a specific embodiment. The chemical mechanical polishing process preferably selectively removes the switching material from the surface region of the second dielectric material in a specific embodiment. In other embodiments, a combination of etch back process and chemical mechanical polishing process may be used. One skilled in the art would recognize other modifications, variations, and alternatives.

Referring now to FIG. 12, the method includes depositing a metal material 1202 overlying the switching material in each of the plurality of via openings. As shown, the metal material 1202 is selectively formed in a portion of the via opening overlying the switching material while the surface region of the second dielectric material is free of the metal material. In a specific embodiment, the metal material at least partially fills each of the plurality of via openings to form a contact region with the switching material in a specific embodiment. In other embodiments, a thin insulating layer (e.g. oxide) is formed prior to the deposition of the metal (e.g. silver) material on top of the undoped amorphous silicon switching material. This interposing thin insulating layer may be naturally or specifically grown or formed, and one or more etch operations (e.g. HF etch, Argon etch) may help control the thickness of this insulating layer. In some embodiments, a thickness of an insulating oxide, prior to deposition of the metal material 1202 may range from about 20 angstroms to about 50 angstroms; in other embodiments, the thickness may range from about 30 angstroms to about 40 angstroms; or the like.

The metal material is selected to have a suitable diffusion characteristic in the presence of an electric field in the amorphous silicon material in a specific embodiment. Depending on the application, the metal material can be silver, gold, platinum, palladium, nickel, aluminum, and others. In a specific embodiment, the metal material is a silver material. A second wiring material 1302 is deposited overlying the metal material. The second wiring material can be a conductor material used in CMOS fabrication. Examples of the conductor material are copper, aluminum, tungsten, including a combination, depending on the embodiment.

In a specific embodiment, the second wiring material is subjected to a third pattern and etch process to form a second wiring structure 1402. Second wiring structure includes metal material 1202 in a specific embodiment. Second wiring structure 1402 is configured to orient in a second direction 1404 at an angle to the first direction and preferably orthogonal to the first direction in a specific embodiment.

In a specific embodiment, the method forms a third dielectric material 1406 overlying the second wiring structure and fills the gaps between the second wiring structures 1402 to isolate the second wiring structures in a specific embodiment.

Referring now to FIG. 14a , a cross sectional view of the non-volatile memory device in the second direction is shown. As shown, the amorphous silicon switching elements are insulated from a neighboring switching element by portions 1408 of the second dielectric material, preventing disturb during operations between neighboring devices in a specific embodiment.

Depending on the embodiment, there can be other variations as illustrated in FIGS. 15-21. For example, the first wiring material can be subjected to a patterning and etching process to form a first wiring structure 1502 separated by gap region 1504 and configured to extend in first direction 1506 as shown in FIG. 15. A second dielectric material 1602 is formed overlying the first wiring structure and fill the gap region to isolate the first wiring structure as shown in FIG. 16. A plurality of via openings 1702 are formed in portions of the second dielectric material to expose a surface region of the first wiring structure. The contact material, for example p+ polysilicon material 1802 is formed in the via openings followed by an undoped amorphous silicon material 1804 (as was described above) as illustrated in FIGS. 18. The amorphous silicon material and the polysilicon material are removed from the surface region of the second dielectric material by an etch back process or a chemical mechanical process including a combination, while the amorphous silicon material and the polysilicon material remain in the via opening in a specific embodiment.

The method selectively forms a metal material 1902 in a portion of the via opening overlying the amorphous silicon material as shown in FIG. 19. As was described above, a thin layer of silicon oxide or other insulator may be disposed on top of the amorphous silicon material prior to the metal material 1902 being deposited. A second wiring material 2002 is formed overlying the metal material as shown in FIG. 20. The second wiring material is subjected to a patterning and etch process to form a plurality of second wiring structure 2102 as shown in FIG. 21. As shown the second wiring structure is spatially configured to extend in a second direction orthogonal to the first direction in a specific embodiment.

FIG. 22 is a simplified cross section view of the non-volatile memory device from the second direction. As shown, as the switching material and the contact material are isolated by portions of the second dielectric material 2202, disturb between neighboring devices from leakage current or parasitic current is therefore prevented during operations of read, write or erase.

In a specific embodiment, a method of forming a non-volatile memory device is provided. The method includes providing a first cell and a second cell in an N by M array of interconnected crossbar structures. The first cell includes a first wiring structure extending in a first direction and a second wiring structure extending in a second direction. The first direction and the second direction are at angle to each other. In a specific embodiment, the first wiring structure is configured to be orthogonal to the second wiring structure, forming a crossbar structure. In a specific embodiment, the first cell includes a contact material overlying the first wiring structure and a switching material overlying the contact material. In a specific embodiment, the contact material can be a p+ polysilicon material and the switching material can include an amorphous silicon material. In a specific embodiment, the first call includes a first amorphous silicon switching region disposed in an intersecting region between the first wiring structure and the second wiring structure. In a specific embodiment, the second cell is formed from the first wiring structure, the switching material, the contact material, and a third wiring structure. The third wiring structure is parallel to the second wiring structure and separated from the second wiring structure in a specific embodiment. In a specific embodiment, a second switching region is dispose in an intersecting region between the first wiring structure and the third wiring structure. At least the switching material and the contact material form a coupling between the first cell and the second cell. The coupling is eliminated by disposing the switching material in a first via structure for the first cell and a second via structure for the second cell. The first via structure and the second via structure are formed in portions of a dielectric material isolated by the dielectric material to electrically and physically isolate at least the first switching region and the second switching region. The dielectric material prevents disturb and crosstalk between the first cell and the second cell when one of the cells is selected in each of the programming, writing, reading or erase cycles in a specific embodiment as illustrated in FIGS. 14a and 22.

In a specific embodiment, a non-volatile memory device is provided. The device includes a substrate having a surface region. A first dielectric material overlying the surface region of the semiconductor substrate. The device includes at least a first cell and a second cell. The first cell and the second cell are provided in an array of N by M interconnected crossbar structure in a specific embodiment. The first cell includes a first wiring structure extending in a first direction overlying the first dielectric material, a first contact region comprising a p+ polysilicon material, a first switching region comprising an amorphous silicon material, and a second wiring structure extending in a second direction orthogonal to the first direction in a specific embodiment. The second cell includes the first wiring structure, a second contact region comprising the p+ polysilicon material, a second switching region comprising the amorphous silicon material, and a third wiring structure. The third wiring structure is separated from the second wiring structure and spatially parallel to the second wiring structure in a specific embodiment. In a specific embodiment, at least the first switching region is configured in a first via structure and at least the second switching region is configured in a second via structure. The first via structure and the second via structure are disposed in portions of a dielectric material. The dielectric material electrically and physically isolate at least the first switching region from the second switching region and prevents cross talk and disturbs between the first cell and the second cell when one of the cells is selected in each of the programming, writing, reading or erase cycles as illustrated in FIGS. 14a and 22.

In another embodiment, A non-volatile memory device structure includes a substrate having a surface region; a first dielectric material overlying the surface region of the semiconductor substrate; a first cell, the first cell comprising a first wiring structure extending in a first direction overlying the first dielectric material, a second wiring structure spatially extending in a second direction orthogonal to the first direction, a first contact region comprising a p+ polysilicon material and a first switching region comprising an amorphous silicon material disposed in a first via structure in a portion of a second dielectric material and in an intersection region between the first wiring structure and the second wiring structure; and a second cell, the second cell comprising the first wiring structure and a third wiring structure separated from the second wiring structure and parallel to the second wiring structure, a second contact region comprising the p+ polysilicon material, a second switching region comprising the amorphous silicon material disposed in a second via structure in a second portion of the second dielectric material, the first via structure comprising the first contact region and the first switching region being physically and electrically isolate from the second via structure comprising the second contact region and the second switching region.

Though the present invention has been described using various examples and embodiments, it is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or alternatives in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims. 

What is claimed is:
 1. A non-volatile memory device structure, comprising: a semiconductor substrate having a surface region; a first dielectric material overlying the surface region of the semiconductor substrate; a first cell comprising a first switching region that comprises a resistive switching material and is disposed between a first bottom electrode and a first top electrode, wherein the first bottom electrode comprises a first portion of a conductive contact layer, wherein the conductive contact layer extends from the first cell to a second cell in a first direction overlying a first wiring structure that extends in the first direction overlying the first dielectric material, wherein the first top electrode is in electrical contact with a second wiring structure extending in a second direction orthogonal to the first direction, wherein the resistive switching material is disposed in a first via structure of a second dielectric material that is in an intersection region between the first wiring structure and the second wiring structure, and wherein the first via structure has sidewalls that are substantially linear over an entire depth of the first via structure; and the second cell comprising a second switching region that comprises the resistive switching material and is disposed between a second bottom electrode and a second top electrode, wherein the second bottom electrode comprises a second portion of the conductive contact layer, wherein the second top electrode is in electrical contact with a third wiring structure separated from and parallel to the second wiring structure, and wherein the first via structure comprising the first switching region is physically and electrically isolated from the second via structure comprising the second switching region; wherein the resistive switching material is configured to support formation of a conductive filament from metal material of the first top electrode or the second top electrode.
 2. The non-volatile memory device structure of claim 1, wherein the first cell and the second cell are provided in an N by M interconnected crossbar array.
 3. The non-volatile memory device structure of claim 1, wherein the first top electrode and the second top electrode comprise a metal material, respectively disposed above the resistive switching material within the first via structure and within the second via structure, wherein the metal material includes a diffusion characteristic into the resistive switching material in the presence of an electric field.
 4. The non-volatile memory device structure of claim 3, wherein the metal material includes metal particles selected from a group consisting of: platinum, palladium, nickel, and aluminum.
 5. The non-volatile memory device structure of claim 1, wherein the conductive contact layer comprises a conductive contact material configured to reduce formation of an interfacial region between the resistive switching material and the first wiring structure.
 6. The non-volatile memory device structure of claim 5, wherein the conductive contact material is substantially free of defect sites that trap conductive particles.
 7. The non-volatile memory device structure of claim 5, wherein the conductive contact material comprises p+ polysilicon material and is configured to reduce a number of defect sites at an interface region between the resistive switching silicon material and the p+ polysilicon material.
 8. The non-volatile memory device structure of claim 7, wherein the resistive switching material comprises an undoped amorphous silicon material and is characterized by a first number of defect sites at regions other than proximate to the interface region, and a second number of defect sites proximate to the interface region wherein the first number is larger than the second number.
 9. The non-volatile memory device structure of claim 1, wherein the first wiring structure comprises tungsten material, copper material, or aluminum material.
 10. The non-volatile memory device structure of claim 1, further comprising an adhesion layer, disposed between the first wiring structure and the first dielectric material, comprising titanium, titanium nitride, tungsten nitride, titanium-material, tungsten-material, or a metal nitride.
 11. A semiconductor device including non-volatile memory device structure, comprising: a semiconductor substrate having a surface region and comprising at least one transistor formed thereon; a first dielectric material disposed above the surface region of the semiconductor substrate and above the at least one transistor; a first wiring structure formed above first portions of the first dielectric material but not above second portions of the first dielectric material, wherein the first wiring structure extends in a first lateral direction; a second dielectric material disposed above the first wiring structure and above the second portions of the first dielectric material; a plurality of vias formed within the second dielectric material, wherein a first via of the plurality of vias exposes a first portion of the first wiring structure and a second via of the plurality of vias exposes a second portion of the first wiring structure, wherein the first via has sidewalls that extend in a substantially straight line from a top of the first via to a bottom of the first via; a first non-volatile memory device disposed in contact with the first portion of the first wiring structure within the first via, wherein the first non-volatile memory device comprises a resistive switching material and a metal material, and wherein the resistive switching material and the metal material substantially fill an entirety of the first via; a second non-volatile memory device disposed in contact with the second portion of the first wiring structure within the second via, wherein the second non-volatile memory device comprises the resistive switching material and the metal material, wherein the first non-volatile memory device is electrically isolated from the second non-volatile memory device; a second wiring structure formed above a first portion of the second dielectric material and in contact with the first non-volatile memory device disposed in the first via, wherein the second wiring structure extends in a second lateral direction, wherein the first lateral direction and the second lateral direction are approximately orthogonal; and a third wiring structure formed above a second portion of the second dielectric material and in contact with the second non-volatile memory device disposed in the second via, wherein the third wiring structure extends in the second lateral direction; wherein the resistive switching material is substantially free of dopants; and wherein the first non-volatile memory device is operably coupled to the at least one transistor.
 12. The semiconductor device of claim 11, wherein the first non-volatile memory device and the second non-volatile memory device are provided in an N by M interconnected crossbar array.
 13. The semiconductor device of claim 11, wherein the metal material includes a diffusion characteristic into the resistive switching material in the presence of an electric field.
 14. The semiconductor device of claim 13, wherein the metal material includes metal particles selected from a group consisting of platinum, palladium, nickel, and aluminum.
 15. The semiconductor device of claim 11, wherein the first non-volatile memory device also comprises a contact material disposed within the first via between the first portion of the first wiring structure and the resistive switching material.
 16. The semiconductor device of claim 15, wherein the contact material is substantially free of defect sites that trap conductive particles.
 17. The semiconductor device of claim 15, wherein the contact material comprises p+ polysilicon material and wherein an interface region between the resistive switching material and the contact material is characterized by a reduced number of defect regions compared to other regions of the resistive switching material.
 18. The semiconductor device of claim 11, wherein the resistive switching material within the first via includes particles of the metal material diffused from the metal material within the first via.
 19. The semiconductor device of claim 11, wherein the first wiring structure comprises a material selected from a group consisting of: tungsten material, copper material, and aluminum material.
 20. The semiconductor device of claim 19, wherein the first wiring structure further comprises an adhesion layer selected from a group consisting of: titanium, titanium nitride, tungsten nitride, titanium-material, tungsten-material, and a metal nitride. 